/////////////////////////////REGISTROS DE COMPARADOR ////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#byte CVRCON=0xFB5 // registro de control del comparador de referencia de voltaje
#bit CVREN=0xFB5.7
#bit CVROE=0xFB5.7
#bit CVRR=0xFB5.7
#bit CVRSS=0xFB5.7
#bit CVR3=0xFB5.7
#bit CVR2=0xFB5.7
#bit CVR1=0xFB5.7
#bit CVR0=0xFB5.7
//CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER ////////////////////////////////////////////////////////////////////////////////
//|CVREN| CVROE| CVRR| CVRSS |CVR3| CVR2| CVR1| CVR0| //
//bit 7 CVREN: Comparator Voltage Reference Enable bit //
// 1 = CVREF circuit powered on //
// 0 = CVREF circuit powered down //
//bit 6 CVROE: Comparator VREF Output Enable bit //
// 1 = CVREF voltage level is also output on the RA0/AN0/CVREF pin //
// 0 = CVREF voltage is disconnected from the RA0/AN0/CVREF pin//
//bit 5 CVRR: Comparator VREF Range Selection bit//
// 1 = 0.00 CVRSRC to 0.625 CVRSRC with CVRSRC/24 step size//
// 0 = 0.25 CVRSRC to 0.719 CVRSRC with CVRSRC/32 step size//
//bit 4 CVRSS: Comparator VREF Source Selection bit//
// 1 = Comparator reference source, CVRSRC = (VREF+) . (VREF-)//
// 0 = Comparator reference source, CVRSRC = VDD . VSS//
//bit 3-0 CVR<3:0>: Comparator VREF Value Selection 0 . CVR3:CVR0 . 15 bits//
// When CVRR = 1://
// CVREF = (CVR3:CVR0/24) . (CVRSRC)//
// When CVRR = 0://
// CVREF = 1/4 . (CVRSRC) + (CVR3:CVR0/32) . (CVRSRC)//
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////REGISTROS DE DATO DE CONVERSION //////////////////////////////////////////////////////////////////////
#byte ADRESH=0xFC4
#byte ADRESL=0xFC3
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#byte CMON=0xFB4 // registro de control de comparador
#bit C2OUT=0xFB4.7
#bit C1OUT=0xFB4.6
#bit C2INV=0xFB4.5
#bit C1INV=0xFB4.4
#bit CIS=0xFB4.3
#bit CM2=0xFB4.2
#bit CM1=0xFB4.1
#bit CM0=0xFB4.0
// CMCON: COMPARATOR CONTROL REGISTER ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// |C2OUT |C1OUT| C2INV |C1INV |CIS |CM2 |CM1| CM0|
//bit 7 C2OUT: Comparator 2 Output bit
// When C2INV = 0:
// 1 = C2 VIN+ > C2 VIN-
// 0 = C2 VIN+ < C2 VINWhen
// C2INV = 1:
// 1 = C2 VIN+ < C2 VIN-
// 0 = C2 VIN+ > C2 VINbit
//bit 6 C1OUT: Comparator 1 Output bit
//When C1INV = 0:
// 1 = C1 VIN+ > C1 VIN-
// 0 = C1 VIN+ < C1 VINWhen
// C1INV = 1:
// 1 = C1 VIN+ < C1 VIN-
// 0 = C1 VIN+ > C1 VINbit
//bit 5 C2INV: Comparator 2 Output Inversion bit
// 1 = C2 output inverted
// 0 = C2 output not inverted
//bit 4 C1INV: Comparator 1 Output Inversion bit
// 1 = C1 output inverted
// 0 = C1 output not inverted
//bit 3 CIS: Comparator Input Switch bit
// When CM2:CM0 = 110:
// 1 = C1 VIN- connects to RD0/PSP0
// C2 VIN- connects to RD2/PSP2
// 0 = C1 VIN- connects to RD1/PSP1
// C2 VIN- connects to RD3/PSP3
//bit 2-0 CM2:CM0: Comparator Mode bits
//
//Legend:
//R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
//-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////// REGISTROS DE A /D /////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#byte ADCON0=0xFC2 // registro de control de A/D CONTROL REGISTER 0
#bit CHS3=0xFC2.5
#bit CHS2=0xFC2.4
#bit CHS1=0xFC2.3
#bit CHS0=0xFC2.2
#bit GO_DONE=0xFC2.1
#bit ADON=0xFC2.0
/* //////////////////////////////////////////////////////////////////////////////////////////////////////////
// ADCON0: A/D CONTROL REGISTER 0
|ADCS1| ADCS0 |CHS2 |CHS1| CHS0| GO/DONE| — |ADON|
bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold)
bit 5-3 CHS2:CHS0: Analog Channel Select bits
000 = Channel 0 (AN0)
001 = Channel 1 (AN1)
010 = Channel 2 (AN2)
011 = Channel 3 (AN3)
100 = Channel 4 (AN4)
101 = Channel 5 (AN5)(1)
110 = Channel 6 (AN6)(1)
111 = Channel 7 (AN7)(1)
Note 1: These channels are unimplemented on PIC18F2X8 (28-pin) devices. Do not select
any unimplemented channel.
bit 2 GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically
cleared by hardware when the A/D conversion is complete)
0 = A/D conversion not in progress
bit 1 Unimplemented: Read as ‘0’
bit 0 ADON: A/D On bit
1 = A/D converter module is powered up
0 = A/D converter module is shut-off and consumes no operating current ////////////////////////////////////////// */
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#byte ADCON1=0xFC1 // registro de control de A/D CONTROL REGISTER 1
#bit VCFG_neg =0xFC1.5
#bit VCFG0_pos =0xFC1.4
#bit PCFG3=0xFC1.3
#bit PCFG2=0xFC1.2
#bit PCFG1=0xFC1.1
#bit PCFG0=0xFC1.0
/* //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
ADCON1: A/D CONTROL REGISTER 1
//////////////////////////////////////////////////////////////////////////////////////////////
|ADFM |ADCS2 |— |— |PCFG3| PCFG2| PCFG1 |PCFG0|
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ‘0’.
bit 6 ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold)
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: On any device Reset, the port pins that are multiplexed with analog functions (ANx)
are forced to be analog inputs.
ADCON1
<ADCS2>
ADCON0
<ADCS1:ADCS0>
Clock Conversion
0 00 FOSC/2
0 01 FOSC/8
0 10 FOSC/32
0 11 FRC (clock derived from the internal A/D RC oscillator)
1 00 FOSC/4
1 01 FOSC/16
1 10 FOSC/64
1 11 FRC (clock derived from the internal A/D RC oscillator)
A = Analog input D = Digital I/O
C/R = # of analog input channels/# of A/D voltage references
Note: Shaded cells indicate channels available only on PIC18F4X8 devices.
PCFG AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF+ VREF- C/R
0000 A A A A A A A A VDD VSS 8/0
0001 A A A A VREF+ A A A AN3 VSS 7/1
0010 D D D A A A A A VDD VSS 5/0
0011 D D D A VREF+ A A A AN3 VSS 4/1
0100 D D D D A D A A VDD VSS 3/0
0101 D D D D VREF+ D A A AN3 VSS 2/1
011x D D D D D D D D — — 0/0
1000 A A A A VREF+ VREF- A A AN3 AN2 6/2
1001 D D A A A A A A VDD VSS 6/0
1010 D D A A VREF+ A A A AN3 VSS 5/1
1011 D D A A VREF+ VREF- A A AN3 AN2 4/2
1100 D D D A VREF+ VREF- A A AN3 AN2 3/2
1101 D D D D VREF+ VREF- A A AN3 AN2 2/2
1110 D D D D D D D A VDD VSS 1/0
1111 D D D D VREF+ VREF- D A AN3 AN2 1/2
A = Analog input D = Digital I/O
C/R = # of analog input channels/# of A/D voltage references
Note: Shaded cells indicate channels available only on PIC18F4X8 devices.
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////*/
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////ADCON2: A/D CONTROL REGISTER 2 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/* |ADFM |— |ACQT2 |ACQT1| ACQT0| ADCS2| ADCS1| ADCS0|
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6 Unimplemented: Read as ‘0’
bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits
111 = 20 TAD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD(1)
bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits
111 = FRC (clock derived from A/D RC oscillator)(1)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.*/
#byte ADCON2=0xFC0
#bit ADFM=0xFC0.7
#bit ACQT2=0xFC0.5
#bit ACQT1=0xFC0.4
#bit ACQT0=0xFC0.3
#bit ADCS2=0xFC0.2
#bit ADCS1=0xFC0.1
#bit ADCS0=0xFC0.0
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///// /////
///// PASOS PARA REALIZAR UNA CONVERSION A/D Y POSTERIOR COMPARACION ////
///// ////
///// /////
///// /////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// 1. Configurar el modulo A/D:
// * configurar pines analogicos/tension de referencia/I/O digitales -> ADCON1
// * seleccionar el canal input A/D -> ADCON0
// * seleccionar clock conversion A/D -> ADCON0
// * activar (ON) el modulo -> ADCON0
//
// 2. Configurar interrupcion A/D, si se desea
// * Clear el bit ADIF
// * setear los bits ADIE, y el bit GIE
//
// 3. Esperar el tiempo de adquisicion requerido
// 4. inicio de la conversion.
// * Set en bit GO/DONE* -> ADCON0
// 5. Esperar para la completa conversion A/D, por lo mismo:
// * Espera de cambios en el bit GO/DONE* para ser cleared o el bit ADIF seteado,
// o
// * Esperar la interrupción A/D
// 6. Leer el resultado del registro A/D (ADRESH:ADRESL), limpiar el bit ADIF, si es necesario.
// 7. Para la siguiente conversion, ir a paso 1 o 2.
//