NOLIST
W = 0
F = 1
; *** Default Device Specifications
; DEVICE 3FFF3FFFh ; All Fuse Bits On
; DEVICE 50101004h ; 14-Bit, 8K Code, 256 EE, ID = 4
; *** DEVICE Device Definitions
PIC16F883 equ 50081003h ; 14-Bit, 4K Code, 256 EE, ID = 3
PIC16F884 equ 50081003h ; 14-Bit, 4K Code, 256 EE, ID = 3
PIC16F886 equ 50101004h ; 14-Bit, 8K Code, 256 EE, ID = 4
PIC16F887 equ 50101004h ; 14-Bit, 8K Code, 256 EE, ID = 4
; *** DEVICE Fuses Definitions
EXTRC equ 3FF80007h ; XX XXXX XXXX X111
EXTRC_OSC_CLKOUT equ 3FF80007h ; XX XXXX XXXX X111
EXTRCIO equ 3FF80006h ; XX XXXX XXXX X110
EXTRC_OSC_NOCLKOUT equ 3FF80006h ; XX XXXX XXXX X110
EXTRC_OSC equ 3FF80006h ; XX XXXX XXXX X110
INTOSC equ 3FF80005h ; XX XXXX XXXX X101
INTRC_OSC_CLKOUT equ 3FF80005h ; XX XXXX XXXX X101
INTOSCIO equ 3FF80004h ; XX XXXX XXXX X100
INTRC_OSC_NOCLKOUT equ 3FF80004h ; XX XXXX XXXX X100
INTRC_OSC equ 3FF80004h ; XX XXXX XXXX X100
EC_OSC equ 3FF80003h ; XX XXXX XXXX X011
HS_OSC equ 3FF80002h ; XX XXXX XXXX X010
XT_OSC equ 3FF80001h ; XX XXXX XXXX X001
LP_OSC equ 3FF80000h ; XX XXXX XXXX X000
WDT_ON equ 3FF70008h ; XX XXXX XXXX 1XXX
WDT_OFF equ 3FF70000h ; XX XXXX XXXX 0XXX
PWRT_OFF equ 3FEF0010h ; XX XXXX XXX1 XXXX
PWRT_ON equ 3FEF0000h ; XX XXXX XXX0 XXXX
MCLR_ON equ 3FDF0020h ; XX XXXX XX1X XXXX
MCLR_OFF equ 3FDF0000h ; XX XXXX XX0X XXXX
PROTECT_ON equ 3FBF0000h ; XX XXXX X0XX XXXX
PROTECT_OFF equ 3FBF0040h ; XX XXXX X1XX XXXX
CPD_ON equ 3F7F0000h ; XX XXXX 0XXX XXXX
CPD_OFF equ 3F7F0080h ; XX XXXX 1XXX XXXX
BOD_ON equ 3CFF0300h ; XX XX11 XXXX XXXX
BOD_NSLEEP equ 3CFF0200h ; XX XX10 XXXX XXXX
BOD_SBODEN equ 3CFF0100h ; XX XX01 XXXX XXXX
BOD_OFF equ 3CFF0000h ; XX XX00 XXXX XXXX
IESO_ON equ 3BFF0400h ; XX X1XX XXXX XXXX
IESO_OFF equ 3BFF0000h ; XX X0XX XXXX XXXX
FCMEN_ON equ 37FF0800h ; XX 1XXX XXXX XXXX
FCMEN_OFF equ 37FF0000h ; XX 0XXX XXXX XXXX
LVP_ON equ 2FFF1000h ; X1 XXXX XXXX XXXX
LVP_OFF equ 2FFF0000h ; X0 XXXX XXXX XXXX
; *** DEVICE2 Fuses Definitions
BOR40V equ 3EFF0100h ; XX XXX1 XXXX XXXX
BOR21V equ 3EFF0000h ; XX XXX0 XXXX XXXX
WRT_OFF equ 39FF0600h ; XX X11X XXXX XXXX
WRT_256 equ 39FF0400h ; XX X10X XXXX XXXX
WRT_1FOURTH equ 39FF0200h ; XX X01X XXXX XXXX
WRT_HALF equ 39FF0000h ; XX X00X XXXX XXXX
; *** Register Names
INDF equ 00h ; Indirect Data
TMR0 equ 01h ; Real Time Clock/Counter
PCL equ 02h ; Program Counter (LSB)
STATUS equ 03h ; Status Flags
FSR equ 04h ; File Select Register
PORTA equ 05h ; Port A Data
PORTB equ 06h ; Port B Data
PORTC equ 07h ; Port C Data
PORTD equ 08h ; Port D Data
PORTE equ 09h ; Port E Data
PCLATH equ 0Ah ; Program Counter (MSB)
INTCON equ 0Bh ; Interrupt Control
PIR1 equ 0Ch ; Peripheral Interrupt Flags 1
PIR2 equ 0Dh ; Peripheral Interrupt Flags 2
TMR1L equ 0Eh ; Timer 1 Data (LSB)
TMR1H equ 0Fh ; Timer 1 Data (MSB)
T1CON equ 10h ; Timer 1 Control
TMR2 equ 11h ; Timer 2 Data
T2CON equ 12h ; Timer 2 Control
SSPBUF equ 13h ; SSP Data
SSPCON equ 14h ; SSP Control
CCPR1L equ 15h ; CCP 1 Data (LSB)
CCPR1H equ 16h ; CCP 1 Data (MSB)
CCP1CON equ 17h ; CCP 1 Control
RCSTA equ 18h ; ASP Status/Control
TXREG equ 19h ; ASP Transmit Data
RCREG equ 1Ah ; ASP Receive Data
CCPR2L equ 1Bh ; CCP 2 Data (LSB)
CCPR2H equ 1Ch ; CCP 2 Data (MSB)
CCP2CON equ 1Dh ; CCP 2 Control
ADRESH equ 1Eh ; A/D Result High
ADRES equ 1Eh ; A/D Result High
ADCON0 equ 1Fh ; A/D Control 0
OPTION_REG equ 81h ; OPTION Register
TRISA equ 85h ; Port A Tristate Control
TRISB equ 86h ; Port B Tristate Control
TRISC equ 87h ; Port C Tristate Control
TRISD equ 88h ; Port D Tristate Control
TRISE equ 89h ; Port E Tristate Control
PIE1 equ 8Ch ; Peripheral Interrupt Enables 1
PIE2 equ 8Dh ; Peripheral Interrupt Enables 2
PCON equ 8Eh ; Power Control
OSCCON equ 8Fh ; Oscillator Control
OSCTUNE equ 90h ; Oscillator Tune
SSPCON2 equ 91h ; SSP Control 2
PR2 equ 92h ; Timer 2 Period
SSPADD equ 93h ; SSP I2C Address
SSPSTAT equ 94h ; SSP Status Flags
WPUB equ 95h ; Weak Pull-Up Register
IOCB equ 96h ; Interrupt-On-Change Register
VRCON equ 97h ; Voltage Reference Control
TXSTA equ 98h ; ASP Transmit Status/Control
SPBRG equ 99h ; ASP Baud Rate
SPBRGH equ 9Ah ; ASP Baud Rate High
PWM1CON equ 9Bh ; PWM 1 Control
ECCPAS equ 9Ch ;
PSTRCON equ 9Dh ; Pulse Steering Control
ADRESL equ 9Eh ; A/D Result Low
ADCON1 equ 9Fh ; A/D Control 1
WDTCON equ 105h ; Watchdog Timer Control
CM1CON0 equ 107h ;
CM2CON0 equ 108h ;
CM2CON1 equ 109h ;
EEDATA equ 10Ch ; EEPROM Data
EEADR equ 10Dh ; EEPROM Address
EEDATH equ 10Eh ; EEPROM Data High
EEADRH equ 10Fh ; EEPROM Address High
SRCON equ 185h ; SR Latch Control
BAUDCTL equ 187h ; ASP Baud Rate Control
ANSEL equ 188h ; Analog Select
ANSELH equ 189h ; Analog Select High
EECON1 equ 18Ch ; EEPROM Control 1
EECON2 equ 18Dh ; EEPROM Control 2
; *** STATUS Bits
C equ 0 ; Carry
DC equ 1 ; Digit (Half) Carry
Z equ 2 ; Zero
PD equ 3 ; Power Down
TO equ 4 ; Time Out
RP0 equ 5 ; Direct Data Page Select 0
RP1 equ 6 ; Direct Data Page Select 1
IRP equ 7 ; Indirect Data Page Select
; *** INTCON Bits
RBIF equ 0 ; PORTB[4..7] Change Interrupt Flag
INTF equ 1 ; RB0/INT Interrupt Flag
TMR0IF equ 2 ; TMR0 Overflow Interrupt Flag
T0IF equ 2 ; TMR0 Overflow Interrupt Flag
RBIE equ 3 ; PORTB[4..7] Change Interrupt Enable
INTE equ 4 ; RB0/INT Interrupt Enable
TMR0IE equ 5 ; TMR0 Overflow Interrupt Enable
T0IE equ 5 ; TMR0 Overflow Interrupt Enable
PEIE equ 6 ; Peripheral Interrupt Enable
GIE equ 7 ; Global Interrupt Enable
; *** PIR1 Bits
TMR1IF equ 0 ; Timer 1 Interrupt Flag
TMR2IF equ 1 ; Timer 2 Interrupt Flag
CCP1IF equ 2 ; CCP 1 Interrupt Flag
SSPIF equ 3 ; SSP Interrupt Flag
TXIF equ 4 ; ASP Transmit Interrupt Flag
RCIF equ 5 ; ASP Receive Interrupt Flag
ADIF equ 6 ; A/D Interrupt Flag
; *** PIR2 Bits
CCP2IF equ 0 ; CCP 2 Interrupt Flag
ULPWUIF equ 2 ;
BCLIF equ 3 ;
EEIF equ 4 ; EEPROM Interrupt Flag
C1IF equ 5 ; Comparator 1 Interrupt Flag
C2IF equ 6 ; Comparator 2 Interrupt Flag
OSPIF equ 7 ;
; *** T1CON Bits
TMR1ON equ 0 ; Timer 1 Enable
TMR1CS equ 1 ; Timer 1 Clock Select
T1SYNC equ 2 ; Timer 1 Sync Enable
T1INSYNC equ 2 ; Timer 1 Sync Enable
NOT_T1SYNC equ 2 ; Timer 1 Sync Enable
T1OSCEN equ 3 ; Timer 1 Oscillator Enable
T1CKPS0 equ 4 ; Timer 1 Prescaler Select (2 Bits)
T1CKPS1 equ 5
; *** T2CON Bits
T2CKPS0 equ 0 ; Timer 2 Prescaler Select (2 Bits)
T2CKPS1 equ 1
TMR2ON equ 2 ; Timer 2 Enable
TOUTPS0 equ 3 ; Timer 2 Postscaler Select (4 Bits)
TOUTPS1 equ 4
TOUTPS2 equ 5
TOUTPS3 equ 6
; *** SSPCON Bits
SSPM0 equ 0 ; SSP Mode Select (4 Bits)
SSPM1 equ 1
SSPM2 equ 2
SSPM3 equ 3
CKP equ 4 ; SSP Clock Polarity Select
SSPEN equ 5 ; SSP Enable
SSPOV equ 6 ; SSP Receive Overflow Flag
WCOL equ 7 ; SSP Write Collision Detect
; *** CCP1CON Bits
CCP1M0 equ 0 ; CCP 1 Mode Select (4 Bits)
CCP1M1 equ 1
CCP1M2 equ 2
CCP1M3 equ 3
CCP1Y equ 4
DC1B0 equ 4
CCP1X equ 5
DC1B1 equ 5
P1M0 equ 6
P1M1 equ 7
; *** RCSTA Bits
RX9D equ 0 ; ASP Received 9th/Parity Bit
OERR equ 1 ; ASP Overrun Flag
FERR equ 2 ; ASP Framing Error Flag
ADDEN equ 3
CREN equ 4 ; ASP Continuous Receive Enable
SREN equ 5 ; ASP Single Receive Enable
RX9 equ 6 ; ASP Receive Data Length Select
SPEN equ 7 ; ASP Enable
; *** CCP2CON Bits
CCP2M0 equ 0 ; CCP 2 Mode Select (4 Bits)
CCP2M1 equ 1
CCP2M2 equ 2
CCP2M3 equ 3
CCP2Y equ 4 ; CCP 2 PWM Bit 0
CCP2X equ 5 ; CCP 2 PWM Bit 1
; *** ADCON0 Bits
ADON equ 0 ; A/D Power Control
GO_DONE equ 1 ; A/D GO/DONE Bit
CHS0 equ 2 ; A/D Channel Select (4 Bits)
CHS1 equ 3
CHS2 equ 4
CHS3 equ 5
ADCS0 equ 6 ; A/D Clock Select (2 Bits)
ADCS1 equ 7
; *** OPTION_REG Bits
PS0 equ 0 ; Prescaler Divisor Select (3 Bits)
PS1 equ 1
PS2 equ 2
PSA equ 3 ; Prescaler Assignment
T0SE equ 4 ; Timer 0 Source Edge Select
T0CS equ 5 ; Timer 0 Clock Source Select
INTEDG equ 6 ; RB0/INT Edge Select
RBPU equ 7 ; Port B Weak Pull-Up Enable
; *** PIE1 Bits
TMR1IE equ 0 ; Timer 1 Interrupt Enable
TMR2IE equ 1 ; Timer 2 Interrupt Enable
CCP1IE equ 2 ; CCP 1 Interrupt Enable
SSPIE equ 3 ; SSP Interrupt Enable
TXIE equ 4 ; ASP Transmit Interrupt Enable
RCIE equ 5 ; ASP Receive Interrupt Enable
ADIE equ 6 ; A/D Interrupt Enable
; *** PIE2 Bits
CCP2IE equ 0 ; CCP 2 Interrupt Enable
ULPWUIE equ 2 ;
BCLIE equ 3 ;
EEIE equ 4 ; EEPROM Interrupt Enable
C1IE equ 5 ; Comparator 1 Interrupt Enable
C2IE equ 6 ; Comparator 2 Interrupt Enable
OSPIE equ 7 ;
; *** PCON Bits
BOD equ 0 ; Brown-Out Detect Flag
NOT_BOR equ 0 ; Brown-Out Detect Flag
NOT_BOD equ 0 ; Brown-Out Detect Flag
POR equ 1 ; Power-On Reset Flag
NOT_POR equ 1 ; Power-On Reset Flag
SBOREN equ 4
ULPWUE equ 5
; *** OSCCON Bits
SCS equ 0
LTS equ 1
HTS equ 2
OSTS equ 3
IRCF0 equ 4
IRCF1 equ 5
IRCF2 equ 6
; *** OSCTUNE Bits
TUN0 equ 0
TUN1 equ 1
TUN2 equ 2
TUN3 equ 3
TUN4 equ 4
; *** SSPCON2 Bits
SEN equ 0
RSEN equ 1
PEN equ 2
RCEN equ 3
ACKEN equ 4
ACKDT equ 5
ACKSTAT equ 6
GCEN equ 7
; *** SSPSTAT Bits
BF equ 0 ; SSP Buffer Full Flag
UA equ 1 ; SSP I2C Update Address Flag
R_W equ 2 ; SSP I2C Read/Write Status
S equ 3 ; SSP I2C Start Flag
P equ 4 ; SSP I2C Stop Flag
D_A equ 5 ; SSP I2C Data/Address Flag
CKE equ 6 ; SSP SPI Clock Edge Select
SMP equ 7 ; SSP SPI Data Input Sample Phase
; *** VRCON Bits
VR0 equ 0 ; VRef Select (4 Bits)
VR1 equ 1
VR2 equ 2
VR3 equ 3
VRR equ 5 ; VRef Range Select
C2VREN equ 6 ; VRef Enable
C1VREN equ 7 ; VRef Enable
; *** TXSTA Bits
TX9D equ 0 ; ASP Transmit 9th Bit
TRMT equ 1 ; ASP Transmit Shift Register Empty
BRGH equ 2 ; ASP High Baud Rate Select
SYNC equ 4 ; ASP Mode Select
TXEN equ 5 ; ASP Transmit Enable
TX9 equ 6 ; ASP Transmit Data Length Select
CSRC equ 7 ; ASP Clock Source Select
; *** PWM1CON Bits
PDC0 equ 0
PDC1 equ 1
PDC2 equ 2
PDC3 equ 3
PDC4 equ 4
PDC5 equ 5
PDC6 equ 6
PRSEN equ 7
; *** ECCPAS Bits
PSSBD0 equ 0
PSSBD1 equ 1
PSSAC0 equ 2
PSSAC1 equ 3
ECCPAS0 equ 4
ECCPAS1 equ 5
ECCPAS2 equ 6
ECCPASE equ 7
; *** PSTRCON Bits
STRA equ 0
STRB equ 1
STRC equ 2
STRD equ 3
STRSYNC equ 4
; *** ADCON1 Bits
VCFG0 equ 4 ; VREF Configuration (2 Bits)
VCFG1 equ 5
ADFM equ 7 ; A/D Result Format Select
; *** WDTCON Bits
SWDTEN equ 0
WDTPS0 equ 1
WDTPS1 equ 2
WDTPS2 equ 3
WDTPS3 equ 4
; *** CM1CON0 Bits
C1CH0 equ 0
C1CH1 equ 1
C1R equ 2
C1POL equ 4
C1OE equ 5
C1OUT equ 6
C1ON equ 7
; *** CM2CON0 Bits
C2CH0 equ 0
C2CH1 equ 1
C2R equ 2
C2POL equ 4
C2OE equ 5
C2OUT equ 6
C2ON equ 7
; *** CM2CON1 Bits
C2SYNC equ 0
T1GSS equ 1
C2RSEL equ 4
C1RSEL equ 5
MC2OUT equ 6
MC1OUT equ 7
; *** SRCON Bits
FVREN equ 0
PULSR equ 2
PULSS equ 3
C2REN equ 4
C1SEN equ 5
SR0 equ 6
SR1 equ 7
; *** BAUDCTL Bits
ABDEN equ 0
WUE equ 1
BRG16 equ 3
SCKP equ 4
RCIDL equ 6
ABDOVF equ 7
; *** EECON1 Bits
RD equ 0 ; EEPROM Read Control
WR equ 1 ; EEPROM Write Control
WREN equ 2 ; EEPROM Write Enable
WRERR equ 3 ; EEPROM Write Error Flag
EEPGD equ 7 ; EEPROM Program / Data Select
LIST