Esto dice el datasheet...
"Master mode operation is supported in firmware using
interrupt generation on the detection of the Start and
Stop conditions. The Stop (P) and Start (S) bits are
cleared from a Reset, or when the SSP module is dis-
abled. The Stop (P) and Start (S) bits will toggle based
on the Start and Stop conditions. Control of the I 2C bus
may be taken when the P bit is set, or the bus is Idle
and both the S and P bits are clear.
In Master mode operation, the SCL and SDA lines are
manipulated in firmware by clearing the corresponding
TRISB<4,1> bit(s). The output level is always low, irre-
spective of the value(s) in PORTB<4,1>. So, when
transmitting data, a ‘1’ data bit must have the
TRISB<1> bit set (input) and a ‘0’ data bit must have
the TRISB<1> bit cleared (output). The same scenario
is true for the SCL line with the TRISB<4> bit. Pull-up
resistors must be provided externally to the SCL and
SDA pins for proper operation of the I2C module."
Por lo poco que entiendo de ingles (que para los datasheet y por el momento me fue suficiente
) parece ser que en modo maestro vos tenés que generar la señales de SDA y SCL manipulando el TRISB. De hecho recomienda la lectura de la siguiente nota
"For more information on Master mode operation, see
Application Note AN554, “Software Implementation of
I2C™ Bus Master”.
