void ENC_WriteReg(char Reg, char Data){
output_low(CS_ENC);
spi_write(WCR|Reg);
spi_write(Data);
output_high(CS_ENC);
}
char ENC_ReadMAC(Char Reg){
char b;
output_low(CS_ENC);
spi_write(RCR|Reg);
spi_write(0x00);
b =spi_read();
output_high(CS_ENC);
return(b);
}
char ENC_ReadETH(char Reg){
char b;
output_low(CS_ENC);
spi_write(RCR|Reg);
b =spi_read();
output_high(CS_ENC);
return(b);
}
void ENC_BFCReg(char Reg,char Data){
output_low(CS_ENC);
spi_write(BFC|Reg);
spi_write(Data);
output_high(CS_ENC);
}
void ENC_BFSReg(char Reg, char Data){
output_low(CS_ENC);
spi_write(BFS|Reg);
spi_write(Data);
output_high(CS_ENC);
}
void ENC_SetBank(char Bank){
ENC_BFCReg(ECON1,0x02);
ENC_BFSReg(ECON1,Bank);
}
void ENCPut(char Data){
output_low(CS_ENC);
spi_write(WBM);
spi_write(Data);
output_high(CS_ENC);
}
char ENCGet(void){
char b;
output_low(CS_ENC);
spi_write(RBM);
b=spi_read();
output_high(CS_ENC);
return(b);
}
void ENC_SendReset(void){
output_low(CS_ENC);
spi_write(SRC);
output_high(CS_ENC);
}
void ENC_GetArray(char *Buffer, long Len){
output_low(CS_ENC);
spi_write(RBM);
while(Len--){
*Buffer++=spi_read();
}
output_high(CS_ENC);
}
void ENC_PutArray(char *Buffer,long Len){
//bufSize += len;
output_low(CS_ENC);
spi_write(WBM);
while(Len--){
spi_write(*Buffer++);
}
output_high(CS_ENC);
}
void ENC_WritePHY(char Reg, long Data){
ENC_SetBank(2);
ENC_WriteReg(MIREGADR,Reg);
ENC_WriteReg(MIWRL,Data);
ENC_WriteReg(MIWRH,(Data>>8));
ENC_SetBank(3);
while(bit_test(ENC_ReadMAC(MISTAT),0));
}
long ENC_ReadPHY(char Reg){
char h,l;
ENC_SetBank(2);
ENC_WriteReg(MIREGADR,Reg);
ENC_WriteReg(MICMD, 0x01);
ENC_SetBank(3);
while(bit_test(ENC_ReadMAC(MISTAT),0));
ENC_SetBank(2);
ENC_WriteReg(MICMD,0x00);
h=ENC_ReadMAC(MIRDH);
l=ENC_ReadMAC(MIRDL);
return(make16(h,l));
}
void Init_ENC(void){
setup_spi(SPI_MASTER | SPI_L_TO_H | SPI_XMIT_L_TO_H);
delay_us(1);
ENC_WritePHY(PHLCON,0b0000110110110000); // configurazione LED (per test)
ENC_SetBank(0);
ENC_WriteReg(ERXSTL,RX_BUF_START); //
ENC_WriteReg(ERXSTH,(RX_BUF_START>>8)); // Inicio Buffer de lectura
ENC_WriteReg(ERXRDPTL,RX_BUF_END); //
ENC_WriteReg(ERXRDPTH,(RX_BUF_END>>8)); // Puntero de Buffer de Lectura
ENC_WriteReg(ERXNDL,RX_BUF_END); //
ENC_WriteReg(ERXNDH,(RX_BUF_END>>8)); // Fin Buffer de Lectura
ENC_WriteReg(ETXSTL,TX_BUF_START); //
ENC_WriteReg(ETXSTH,(TX_BUF_START>>8)); // Incicio de Buffer de Escritura.-
ENC_SetBank(2);
ENC_WriteReg(MACON1,0x0D); // MARXEN TXPAUS RXPAUS
ENC_WriteReg(MACON3,0x30); // Half Duplex, Padding 60byte, CRC
ENC_WriteReg(MAIPGL,0x12); //
ENC_WriteReg(MAIPGH,0x0C); //
ENC_WriteReg(MABBIPG,0x12); // Inter-Packet Gap
ENC_WriteReg(MAMXFLL,1500);
ENC_WriteReg(MAMXFLH,(1500>>8));
ENC_SetBank(3);
ENC_WriteReg(MAADR1, MY_MAC1);
ENC_WriteReg(MAADR2, MY_MAC2);
ENC_WriteReg(MAADR3, MY_MAC3);
ENC_WriteReg(MAADR4, MY_MAC4);
ENC_WriteReg(MAADR5, MY_MAC5);
ENC_WriteReg(MAADR6, MY_MAC6);
ENC_WritePHY(PHCON2,0b0000000100000000); // disabilita il loopback
ENC_WritePHY(PHCON1,0); // habilita il PHY
ENC_SetBank(1);
ENC_WriteReg(ERXFCON,0b10100001); // imposta i filtri di ricezione
ENC_BFSReg(ECON1,0b100); // abilita la ricezione
ENC_WriteReg(EIR,0);
ENC_WriteReg(EIE,0b11000000); // abilita l'interrupt RX
}