; Upon power up or reset, this program starts sampling pin ra.0 and recording its
; state in sequential addresses of a 1Mb dynamic RAM. When the DRAM is full, the
; program plays back the recorded bits in a continuous loop.
; Remember to change device info when programming part.
device pic16c55,xt_osc,wdt_off,protect_off
reset start
Sin = ra.0 ; Signal generator input
RAS = ra.1 ; DRAM row-address strobe
WR = ra.2 ; DRAM write line (0 = write)
Dout = ra.3 ; DRAM data line
adrb_lo = rb ; Low bits of address bus
adrb_hi = rc ; High bits of address bus
Din = rc.2 ; DRAM Q line
CAS = rc.3 ; DRAM column-address strobe
Sout = rc.5 ; Signal out to speaker
; Put variable storage above special-purpose registers.
org 8
r_ctr ds 1 ; Refresh counter
row_lo ds 1 ; Eight LSBs of row address
row_hi ds 1 ; Two MSBs of row address
col_lo ds 1 ; Eight LSBs of column address
col_hi ds 1 ; Two MSBs of column address
flags ds 1 ; Holder for bit variable flag
flag = flags.0 ; Overflow flag for 20-bit address
; Set starting point in program ROM to zero
org 0
start setb RAS ; Disable RAS and CAS before
setb CAS ; setting ports to output.
mov !ra,#1 ; Make ra.0 (Sin) an input.
mov !rb,#0 ; Make rb (low addresses) output.
mov !rc,#00000100b ; Make rc.2 (Din) an input.
clr flags ; Clear the variables.
clr row_lo
clr row_hi
clr col_lo
clr col_hi
call refresh ; Initialize DRAM.
:record call refresh ; Refresh the DRAM.
call write ; Write Sin bit to DRAM.
call inc_xy ; Increment row and col
; addresses.
jnb flag,:record ; Repeat until address overflows.
:play call refresh ; Refresh the DRAM.
call read ; Retrieve bit and write to Sout)
call inc_xy ; Increment row and col
; addresses.
goto :play ; Loop until reset.
write mov adrb_lo,row_lo ; Put LSBs of row addr on bus
(rb).
AND adrb_hi,#11111100b ; Clear bits adrb_hi.0 and .1.
OR adrb_hi,row_hi ; Put MSBs of row adr on bus (rc).
clrb RAS ; Strobe in the row address.
movb Dout,Sin ; Supply the input bit to the
DRAM,
movb Sout,Sin ; and echo it to the speaker.
mov adrb_lo,col_lo ; Put LSBs of col addr on bus (rb).
AND adrb_hi,#11111100b ; Clear bits adrb_hi.0 and .1.
OR adrb_hi,col_hi ; Put MSBs of col addr on bus
(rc).
clrb WR ; Set up to write.
clrb CAS ; Strobe in the column address.
setb WR ; Conclude the transaction by
setb RAS ; restoring WR, RAS, & CAS high
setb CAS ; (inactive).
ret
read mov adrb_lo,row_lo ; Put LSBs of row addr on bus
(rb).
AND adrb_hi,#11111100b ; Clear bits adrb_hi.0 and .1.
OR adrb_hi,row_hi ; Put MSBs of row addr on bus
(rc)
clrb RAS ; Strobe in the row address.
mov adrb_lo,col_lo ; Put LSBs of col addr on bus (rb).
AND adrb_hi,#11111100b ; Clear bits adrb_hi.0 and .1.
OR adrb_hi,col_hi ; Put MSBs of col addr on bus
(rc).
clrb CAS ; Strobe in the column address.
movb Sout,Din ; Copy the DRAM data to the
; speaker.
setb RAS ; Conclude transaction by
; restoring
setb CAS ; RAS and CAS high (inactive).
ret