0 Usuarios y 1 Visitante están viendo este tema.
#FUSES NOWDT //No Watch Dog Timer #FUSES WDT128 //Watch Dog Timer uses 1:128 Postscale #FUSES INTRC_IO //Internal RC Osc, no CLKOUT #FUSES NOPLLEN //4X HW PLL disabled, 4X PLL enabled in software #FUSES NOFCMEN //Fail-safe clock monitor disabled #FUSES NOIESO //Internal External Switch Over mode disabled #FUSES NOBROWNOUT //No brownout reset #FUSES WDT_SW //No Watch Dog Timer, enabled in Software #FUSES NOPBADEN //PORTB pins are configured as digital I/O on RESET #FUSES NOMCLR //Master Clear pin used for I/O #FUSES NOSTVREN //Stack full/underflow will not cause reset #FUSES NOLVP //No low voltage prgming, B3(PIC16) or B5(PIC18) used for I/O #FUSES NOXINST //Extended set extension and Indexed Addressing mode disabled (Legacy mode) #use delay(clock=64M) main(){ setup_oscillator(OSC_64MHZ|OSC_INTRC|OSC_PLL_OFF); }
#int_TIMER1 void TIMER1_isr(void){ // cont++; // if(cont == 2){ // 0,5*1=1 seg ban_1seg = 1;cont = 0; } set_timer1(-934464); // 0.5=4/64000000*8(65536-x),x=-934464 }
#include <18F26K22.h> #FUSES NOWDT //No Watch Dog Timer #FUSES INTRC_IO //Internal RC Osc, no CLKOUT #FUSES NOPLLEN //4X HW PLL disabled, 4X PLL enabled in software #FUSES NOFCMEN //Fail-safe clock monitor disabled #FUSES NOIESO //Internal External Switch Over mode disabled #FUSES NOBROWNOUT //No brownout reset #FUSES WDT_SW //No Watch Dog Timer, enabled in Software #FUSES NOPBADEN //PORTB pins are configured as digital I/O on RESET #FUSES NOMCLR //Master Clear pin used for I/O #FUSES STVREN //Stack full/underflow will cause reset #FUSES NOLVP //No low voltage prgming, B3(PIC16) or B5(PIC18) used for I/O #FUSES NOXINST //Extended set extension and Indexed Addressing mode disabled (Legacy mode) #use delay(clock=64M, internal=16MHz)
void main(void) { setup_oscillator(OSC_64MHZ | OSC_INTRC); }
#INCLUDE <18F26k22.h> #FUSES INTRC_IO, PLLEN, PRIMARY, TIMER3B5, NOWDT, NOHFOFST, NOIESO, PUT, MCLR, BROWNOUT, BORV22, WDT4096, NOLVP, NOCPD, PROTECT, CPB#USE DELAY (CLOCK = 64 000 000)
// CONFIG1H#pragma config FOSC = INTIO7 // Oscillator Selection bits (Internal oscillator block, CLKOUT function on OSC2)#pragma config PLLCFG = OFF // 4X PLL Enable (Oscillator used directly)#pragma config PRICLKEN = OFF // Primary clock enable bit (Primary clock can be disabled by software)#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)#pragma config IESO = ON // Internal/External Oscillator Switchover bit (Oscillator Switchover mode enabled)int main(int argc, char** argv){ OSCCONbits.IRCF = 0b111; // 16 mhz oscilador interno OSCTUNEbits.PLLEN = 0; TRISC = 0; LATCbits.LATC4 = 0; while (1) { LATCbits.LATC4 ^= 1; }}
// CONFIG1H#pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block)#pragma config PLLCFG = ON // 4X PLL Enable (Oscillator multiplied by 4)#pragma config PRICLKEN = OFF // Primary clock enable bit (Primary clock can be disabled by software)#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)#pragma config IESO = ON // Internal/External Oscillator Switchover bit (Oscillator Switchover mode enabled)
when internal clock modes are enabled, the PLL can only be controlled through software. The PLLEN control bit of the OSCTUNE register is used to enable or disable the PLL operation when the HFINTOSC is used.
Tengo unas contradicciones con lo que hay en el datasheet.Por una parte:El PLLCFG si importa (especialmente cuando lo pones con que los pines de OSC funcionen como salida, ya que el ultimo bit es 0), tenes la figura un poquito mas arriba de la tabla, si la salida de la AND de la palabra de configuracion y el PLLCFG es 1, tendrias un 1 siempre en PLL_Select, por mas que modifiques PLLEN, ya que termina siendo una OR entre estos 2 ultimos valores. Lo que lleva a algo mas raro, cuando tenes salida al exterior, si o si la habilitacion es por software y no en los fuses.Por otra parte:Citarwhen internal clock modes are enabled, the PLL can only be controlled through software. The PLLEN control bit of the OSCTUNE register is used to enable or disable the PLL operation when the HFINTOSC is used. Aca deja claro que si o si se debe activar con el PLLENPero lo que mas me molesta es que teniendo un bit que se llame PLLEN,bit 6 PLLEN: Frequency Multiplier 4xPLL for HFINTOSC Enable bit(1)1 = PLL enabled0 = PLL disabledEn el que con un 1 se HABILITA, y si luego seguis la logica, ese multiplexor esta mal, o estan intercambiados los valores de 0 y 1. Debe existir un error en el datasheet, y no esta documentado el error. Busque y no aparece en los errata