Ram Dinamica

[nicola]

Buenas buenas, estuve buscando informacion sobre como usar ram dinamicas y no tuve mucha suerte...
La cuestion seria esta: poder manejar una ram dinamica (desde una misera 4164 a una de 4 megas) con un programa en C.
En CCS hay unas librerias que no me dieron mucho exito (4264.h y 4264.c), compilan y en teoria todo esta bien, pero cuando lo pruebo en el proto, no pasa nada.

Lo mas concreto que encontre en la red es este pdf:
http://www.tech-tools.com/hwt12.htm
deberia llamarse "dram for dummies", pero sin embargo no termino de entender el programa porqe esta en assembly.
Alguno me podria dar una mano, o tirar una punta por la cual avanzar?

Se agradece de antemano  

Código: ASM

1. ; Upon power up or reset, this program starts sampling pin ra.0 and recording its
2. ; state in sequential addresses of a 1Mb dynamic RAM. When the DRAM is full, the
3. ; program plays back the recorded bits in a continuous loop.
4. ; Remember to change device info when programming part.
5. device pic16c55,xt_osc,wdt_off,protect_off
6. reset start
7. Sin = ra.0 ; Signal generator input
8. RAS = ra.1 ; DRAM row-address strobe
9. WR = ra.2 ; DRAM write line (0 = write)
10. Dout = ra.3 ; DRAM data line
11. adrb_lo = rb ; Low bits of address bus
12. adrb_hi = rc ; High bits of address bus
13. Din = rc.2 ; DRAM Q line
14. CAS = rc.3 ; DRAM column-address strobe
15. Sout = rc.5 ; Signal out to speaker
16. ; Put variable storage above special-purpose registers.
17. org 8
18.  
19. r_ctr ds 1 ; Refresh counter
20. row_lo ds 1 ; Eight LSBs of row address
21. row_hi ds 1 ; Two MSBs of row address
22. col_lo ds 1 ; Eight LSBs of column address
23. col_hi ds 1 ; Two MSBs of column address
24. flags ds 1 ; Holder for bit variable flag
25. flag = flags.0 ; Overflow flag for 20-bit address
26. ; Set starting point in program ROM to zero
27. org 0
28. start setb RAS ; Disable RAS and CAS before
29. setb CAS ; setting ports to output.
30. mov !ra,#1 ; Make ra.0 (Sin) an input.
31. mov !rb,#0 ; Make rb (low addresses) output.
32. mov !rc,#00000100b ; Make rc.2 (Din) an input.
33. clr flags ; Clear the variables.
34. clr row_lo
35. clr row_hi
36. clr col_lo
37. clr col_hi
38. call refresh ; Initialize DRAM.
39. :record call refresh ; Refresh the DRAM.
40. call write ; Write Sin bit to DRAM.
41. call inc_xy ; Increment row and col
42. ; addresses.
43. jnb flag,:record ; Repeat until address overflows.
44. :play call refresh ; Refresh the DRAM.
45. call read ; Retrieve bit and write to Sout)
46. call inc_xy ; Increment row and col
47. ; addresses.
48. goto :play ; Loop until reset.
49. write mov adrb_lo,row_lo ; Put LSBs of row addr on bus
50. (rb).
51. AND adrb_hi,#11111100b ; Clear bits adrb_hi.0 and .1.
52. OR adrb_hi,row_hi ; Put MSBs of row adr on bus (rc).
53. clrb RAS ; Strobe in the row address.
54. movb Dout,Sin ; Supply the input bit to the
55. DRAM,
56. movb Sout,Sin ; and echo it to the speaker.
57. mov adrb_lo,col_lo ; Put LSBs of col addr on bus (rb).
58. AND adrb_hi,#11111100b ; Clear bits adrb_hi.0 and .1.
59. OR adrb_hi,col_hi ; Put MSBs of col addr on bus
60. (rc).
61. clrb WR ; Set up to write.
62. clrb CAS ; Strobe in the column address.
63. setb WR ; Conclude the transaction by
64. setb RAS ; restoring WR, RAS, & CAS high
65. setb CAS ; (inactive).
66. ret
67. read mov adrb_lo,row_lo ; Put LSBs of row addr on bus
68. (rb).
69. AND adrb_hi,#11111100b ; Clear bits adrb_hi.0 and .1.
70. OR adrb_hi,row_hi ; Put MSBs of row addr on bus
71. (rc)
72. clrb RAS ; Strobe in the row address.
73. mov adrb_lo,col_lo ; Put LSBs of col addr on bus (rb).
74. AND adrb_hi,#11111100b ; Clear bits adrb_hi.0 and .1.
75. OR adrb_hi,col_hi ; Put MSBs of col addr on bus
76. (rc).
77. clrb CAS ; Strobe in the column address.
78. movb Sout,Din ; Copy the DRAM data to the
79. ; speaker.
80. setb RAS ; Conclude transaction by
81. ; restoring
82. setb CAS ; RAS and CAS high (inactive).
83. ret

pd: una cuestion que veo en la libreria de ccs es que hay algo raro con el refresh de la memoria...cuando deshabilita las interrupciones frena la del timer 0 y despues arranca la del timer 0, sin embargo el timer para dispararse cada 4ms es el timer 1 

Código: C

1. // the timer will interrupt every 4ms inorder to refresh the
2. // memory
3. #int_timer1
4. void Refresh ( )
5. {
6.    unsigned int16 i;
7.    // to output, CAS must be high, then each row is output followed
8.    // by an RAS cycle
9.    output_high(RAS);
10.    output_high(CAS);
11.    for(i=0;i<0x100;i++)
12.    {
13.       addressByte(i);
14.       output_low(RAS);
15.       output_high(RAS);
16.    }
17.    // set the timer up so that it will role over in 4ms
18.    set_timer1(0xC800);
19. }
20.  
21.  
22. // BitRead will return the bit located at the address desired
23. //    rowAddress = the row number of the bit
24. //    colAddress = the column number of the bit
25. //
26. // Events needed to read one
27. //    1. output row address to the chip
28. //    2. latch row address by bringing RAS low
29. //    3. bring write enable high
30. //    4. output column address to the chip
31. //    5. latch row address by bringing CAS low
32. //    6. read data in
33. //    7. bring CAS high
34. //    8. bring RAS high
35. int1 BitRead ( int rowAddress, int colAddress )
36. {
37.    int1 data;
38.  
39.    disable_interrupts(global);
40.    disable_interrupts(int_timer0);
41.  
42.    output_high(RAS);
43.    output_high(CAS);
44.  
45.    addressByte(rowAddress);
46.    #asm nop #endasm
47.    output_low(RAS);
48.  
49.    output_high(WE);
50.    addressByte(colAddress);
51.    #asm nop #endasm
52.    output_low(CAS);
53.  
54.    data = input(D0);
55.  
56.    output_high(CAS);
57.    output_high(RAS);
58.  
59.    enable_interrupts(int_timer0);
60.    enable_interrupts(global);
61.  
62.    return data;
63. }