¿Dónde están los #fuses?

[LoPiTaL]

Supongo que estará en algún rincón del foro, pero no lo encuentro. Tengo dos preguntas, a ver si alguien me puede ayudar:

1.- ¿Qué hace #fuses PUT?

2.- ¿Dónde encuentro todas los parámetros que hay para configurar el programador, con su descripción y lo que hacen?

Si sirve de algo, uso un pic 18f2550.

Gracias de antemano,

LoPiTaL

[RedPic]

PUT es el Power Up Timer y como casi toda la información la puedes encontrar en el Datasheet del micro. Y por supuesto que sirve de algo el modelo ya que modelos distintos tienes fuses distintos.

Te pego algo del Datasheet del 18F2550 (y compatibles)

Pagina 35.

The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table 28-12). It is enabled by clearing (= 0) the PWRTEN configuration bit.

Pagina 48:

If the Power-up Timer is enabled, it will be invoked after VDD rises above VBOR; it then will keep the chip in
Reset for an additional time delay, TPWRT (parameter 33, Table 28-12). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay.

Pagina 49:

4.5.1 POWER-UP TIMER (PWRT)
The Power-up Timer (PWRT) of PIC18F2455/2550/4455/4550 devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 μs = 65.6ms. While the PWRT is counting, the device is held in Reset.

The power-up time delay depends on the INTRC clock and will vary from chip to chip due to temperature and
process variation. See DC parameter 33 (Table 28-12) for details.

The PWRT is enabled by clearing the PWRTEN configuration bit.

... y siguientes.

[LoPiTaL]

Ahhh muchas gracias, ya está claro.

Pero sigo teniendo la duda de dónde están (o cómo saber cuáles son)las abreviaturas a usar en el programa. Es decir, por ejemplo: para usar un reloj externo con RA6 como puerto de I/O, en el datasheet sale como ECIO (pag 25). Sin embargo, al hacer #fuses ECIO, el compilador (MPLAB con CCS) me da un error, diciéndome que no reconoce ECIO. He mirado el manual de CCS y no lo he visto en ninguna parte.

Muchas gracias por responder tan rápido, y sigo esperando respuestas,

LoPiTaL

[RedPic]

Si, y solo si, usas el compilador CCS C ...

Ahí tienes donde están todos los #fuses aunque imagino que conocerás tu compilador y no te estoy diciendo nada nuevo ...

[LoPiTaL]

Ahhh eso era eso era!!!! Muchas gracias!!!

Solo una ultima cosita con este tema (ya se que me estoy poniendo pesado.... ): yo utilizo el programa MPLAB más que el CCS Compiler (tengo el plug-in instalado y tal), ¿se puede tener acceso a esa información sin tener que habrir el otro programa?

De nuevo, muchísimas gracias por la ayuda!!!

LoPiTaL

[RedPic]

En el directorio de instalación del CCS C tienes un fichero de texto fuses.txt con TODOS los fuses de TODOS los Pics ...

ABW20 20-bit Address bus
ABW16 16-bit Address bus
ABW12 12-bit Address bus
ABW8 8-bit Address bus
BANDGAPLOW Lowest Bandgap voltage
BANDGAPHIGH Highest Bandgap voltage
BBSIZ1K 1K words Boot Block size
BBSIZ2K 2K words Boot Block size
BBSIZ4K 4K words Boot Block size
BORSEN See Datasheet
BORV20 Brownout reset at 2.0V
BORV21 Brownout reset at 2.1V
BORV25 Brownout reset at 2.5V
BORV27 Brownout reset at 2.7V
BORV28 Brownout reset at 2.8V
BORV40 Brownout reset at 4.0V
BORV42 Brownout reset at 4.2V
BORV43 Brownout reset at 4.3V
BORV45 Brownout reset at 4.5V
BORV46 Brownout reset at 4.6V
BROWNOUT Reset when brownout detected
BROWNOUT_NOSL Brownout enabled during operation, disabled during SLEEP
BROWNOUT_SW Brownout controlled by configuration bit in special file register
BW8 8-bit external bus mode
BW16 16-bit external bus mode
CCPB0 CCP1 input/output multiplexed with RB0
CCPB2 CCP1 input/output multiplexed with RB2
CCPB3 CCP1 input/output multiplexed with RB3
CCP2B3 CCP2 input/output multiplexed with RB3
CCP2C1 CCP2 input/output multiplexed with RC1
CCP2E7 CCP2 input/output multiplexed with RE7
CLKOUT Output clock on OSC2
CPB Boot Block Code Protected
CPD Data EEPROM Code Protected
CPU Microprocessor Mode
CPU_BB Microprocessor with Boot Block mode
DEBUG Debug mode for use with ICD
DPROTECT Protect EE memory
E4_IO External clock with HW enabled 4X PLL
E4_SW_IO External Clock with SW enabled 4x PLL
EBTR Memory protected from table reads
EBTRB Boot block protected from table reads
EC External clock with CLKOUT
EC_IO External clock
ECCPE Enhanced CCP PWM outpts multiplexed with RE6 thorugh RE3
ECCPH Enhanced CCP PWM outpts multiplexed with RH7 thorugh RH4
EMCU Extended Microcontroller mode
ER External resistor osc, with CLKOUT
ER_IO External resistor osc
FCMEN Fail-safe clock monitor enabled
FLTAC1 FLTA input is multiplexed with RC1
FLTAD4 FLTA input is multiplexed with RD4
H4 High speed osc with HW enabled 4X PLL
H4_SW High speed osc with SW enabled 4x PLL
HPOL_HIGH High-Side Transistors Polarity is Active-High (PWM 1,3,5 and 7)
HPOL_LOW High-Side Transistors Polarity is Active-Low (PWM 1,3,5 and 7)
HS High speed Osc (> 4mhz)
IESO Internal External Switch Over mode enabled
INT125KHZ Internal 125 khz Osc
INT1MHZ Internal 1 mhz Osc
INT250KHZ Internal 250 khz Osc
INT2MHZ Internal 2 mhz Osc
INT31KHZ Internal 31 khz Osc
INT4MHZ Internal 4 mhz Osc
INT500KHZ Internal 500 khz Osc
INT62KHZ Internal 62 khz Osc
INTRC Internal RC Osc
INTRC_IO Internal RC Osc, no CLKOUT
LP Low power osc < 200 khz
LPOL_HIGH Low-Side Transistors Polarity is Active-High (PWM 0,2,4 and 6)
LPOL_LOW Low-Side Transistors Polarity is Active-Low (PWM 0,2,4 and 6)
LPT1OSC Timer1 configured for low-power operation
LVP Low Voltage Programming on B3(PIC16) or B5(PIC18)
MCLR Master Clear pin enabled
MCU Microcontroller Mode
NOBORSEN See Datasheet
NOBROWNOUT No brownout reset
NOCPB No Boot Block code protection
NOCPD No EE protection
NODEBUG No Debug mode for ICD
NODPROTECT No code protection
NOEBTR Memory not protected from table reads
NOEBTRB Boot block not protected from table reads
NOFCMEN Fail-safe clock monitor disabled
NOIESO Internal External Switch Over mode disabled
NOLPT1OSC Timer1 configured for higher power operation
NOLVP No low voltage prgming, B3(PIC16) or B5(PIC18) used for I/O
NOMCLR  Master Clear pin used for I/O
NOOSCSEN Oscillator switching is disabled, main oscillator is source
NOPARITY No memory parity checking
NOPBADEN PORTB pins are configured as digital I/O on RESET
NOPROTECT Code not protected from reading
NOPUT No Power Up Timer
NOPWMPIN PWM outputs drive active state upon Reset
NOSTVREN Stack full/underflow will not cause reset
NOSYNC No sync between I/O and clock
NOTR Table reads disabled
NOTW Table writes disabled
NOWAIT Wait selections unavailable for Table Reads or Table Writes
NOWDT No Watch Dog Timer
NOWDTLD No long delay on WDT Postscale
NOWINEN WDT Timer Window Disabled
NOWRT Program memory not write protected
NOWRTD Data EEPROM not write protected
NOWRTB Boot block not write protected
NOWRTC configuration not registers write protected
NOWURE Wake-up and continue
NOXINST Extended set extension and Indexed Addressing mode disabled (Legacy mode)
OSCSEN Oscillator switching is enabled
PARITY Memory parity checking on
PBADEN PORTB pins are configured as analog input channels on RESET
PROTECT Code protected from reads
PROTECT_5% Protect 5% of ROM
PROTECT_50% Protect 50% of ROM
PROTECT_75% Protect 75% of ROM
PROTECT_88% Protect 88% of ROM
PROTECT_CAL  Prevent reading of calibration area
PROTECT_CODE Prevent reading of code
PROTECT_USER Prevent reading of user area
PUT Power Up Timer
PWMPIN PWM outputs disabled upon Reset
RB4 B4 is an I/O pin not CLKOUT
RC  Resistor/Capacitor Osc with CLKOUT
RC_IO Resistor/Capacitor Osc
SSP_RC SCK/SCL=RC5, SDA/SDI=RC4, SDO=RC7
SSP_RD SCK/SCL=RD3, SDA/SDI=RD2, SDO=RD1
STVREN Stack full/underflow will cause reset
SYNC Sync I/O with clock
T1LOWPOWER Timer1 low power operation when in sleep
T1STANDARD Timer1 standard (legacy) oscillator operation
TR Table reads allowed
TW Table writes allowed
WAIT Wait selections for Table Reads and Table Writes
WDT Watch Dog Timer
WDT1 Watch Dog Timer uses 1:1 Postscale
WDT2 Watch Dog Timer uses 1:2 Postscale
WDT4 Watch Dog Timer uses 1:4 Postscale
WDT8 Watch Dog Timer uses 1:8 Postscale
WDT16 Watch Dog Timer uses 1:16 Postscale
WDT32 Watch Dog Timer uses 1:32 Postscale
WDT64 Watch Dog Timer uses 1:64 Postscale
WDT128 Watch Dog Timer uses 1:128 Postscale
WDT256 Watch Dog Timer uses 1:256 Postscale
WDT512 Watch Dog Timer uses 1:512 Postscale
WDT1024 Watch Dog Timer uses 1:1024 Postscale
WDT2048 Watch Dog Timer uses 1:2048 Postscale
WDT4096 Watch Dog Timer uses 1:4096 Postscale
WDT8192 Watch Dog Timer uses 1:8192 Postscale
WDT16384 Watch Dog Timer uses 1:16384 Postscale
WDT32768 Watch Dog Timer uses 1:32768 Postscale
WDTLD Watch Dog Timer with long delay (16x Postscale)
WINEN WDT Timer Window Enabled
WRT Program Memory Write Protected
WRT_50% Lower half of Program Memory is Write Protected
WRT_25% Lower quarter of Program Memory is Write Protected
WRT_5% Lower 255 bytes of Program Memory is Write Protected
WRTD Data EEPROM write protected
WRTB Boot block write protected
WRTC configuration registers write protected
WURE Wake up and Reset
XINST Extended set extension and Indexed Addressing mode enabled
XT Crystal osc <= 4mhz
X4 XT Oscillator, PLL enabled
E4 EC Oscillator, PLL enabled, with CLKOUT
INTXT Internal Oscillator, XT used by USB
INTHS Internal Oscillator, HS used by USB
PLL1 No PLL PreScaler
PLL2 Divide By 2(8MHz oscillator input)
PLL3 Divide By 3(12MHz oscillator input)
PLL4 Divide By 4(16MHz oscillator input)
PLL5 Divide By 5(20MHz oscillator input)
PLL6 Divide By 6(24MHz oscillator input)
PLL10 Divide By 10(40MHz oscillator input)
PLL12 Divide By 12(48MHz oscillator input)
CPUDIV1 No System Clock Postscaler
CPUDIV2 System Clock by 2
CPUDIV3 System Clock by 3
CPUDIV4 System Clock by 4
USBDIV USB clock source comes from PLL divide by 2
NOUSBDIV USB clock source comes from primary oscillator
VREGEN USB voltage regulator enabled
NOVREGEN USB voltage regulator disabled
ICPRT ICPRT enabled
NOICPRT ICPRT disabled
XTPLL Crystal/Resonator with PLL enabled
HSPLL High Speed Crystal/Resonator with PLL enabled
ECPLL External Clock with PLL enabled and Fosc/4 on RA6
ECPIO External Clock with PLL enabled, I/O on RA6
PRIMARY Primary clock is system clock when scs=00
EMCU12 Extended microcontroller mode,12 bit address mode
EMCU16 Extended microcontroller mode,16 bit address mode
EMCU20 Extended microcontroller mode,20 bit address mode
EASHFT Address shifting enabled
NOEASHFT Address shifting disabled
IOSC4 INTOSC speed 4 MHz
IOSC8 INTOSC speed 8MHz
PWM4B5 PWM4 output is multiplexed on RB5
PWM4D5 PWM4 output is multiplexed on RD5
EXCLKC3 TMR0/T5CKI external clock input is muliplexed with RC3
EXCLKD0 TMR0/T5CKI external clock input is muliplexed with RD0